1. Field of the invention
The present invention relates to a digital frequency multiplying circuit, and more specifically to a digital frequency multiplying circuit capable of generating a pulse having a desired pulse width without being influenced by fluctuation in a manufacturing process and variation in environment.
2. Description of related art
Referring to FIG. 18A, which illustrates a general example of the prior art digital frequency multiplying circuit, the shown digital frequency multiplying circuit includes a plurality of delays dl1 to dln cascaded between an input terminal for receiving a clock CK and one input of an exclusive-OR circuit (called an "EX-OR circuit" hereinafter) EXR3, the other input of the EX-OR circuit EXR3 being connected directly to the clock input terminal, so that a frequency-multiplied signal CK2F is obtained from the EX-OR circuit EXR3.
Referring to FIG. 18A and FIG. 18B which is a timing chart illustrating an operation of the digital frequency multiplying circuit shown in FIG. 18A, the clock signal CK is delayed by the delays dl1 to dln which are constituted of an even number of inverters, so that a delayed signal CLK is obtained. Here, an ideal delay time means that assuming that the period of a logical high level (called "1" hereinafter) of the clock signal CK is "T", a delay time from the moment the clock signal CK rises up from a logical low level (called "0" hereinafter) to "1" to the moment the delayed clock signal CKD rises up from "0" to "1" is T/2. This delayed clock signal CKD and the clock signal CK is exclusive-ORed in the EX-OR circuit EXR3, so that a signal CK2A having double the frequency of the clock signal CK is outputted from the EX-OR circuit EXR3 as the signal CK2F.
In this digital frequency multiplying circuit, the pulse width of the frequency-multiplied signal is determined by the delay time of the inverters constituting the delay. This delay time is determined at the time of design in accordance with a desired pulse width, and is greatly influenced by fluctuation in a manufacturing process of a semiconductor integrated circuit and variation in environment. Therefore, when the delay time from the rising of the clock signal CK to the rising of the delayed clock signal CKD becomes larger than T/2, a frequency-multiplied signal CK2B as shown in FIG. 18B is obtained from the EX-OR circuit EXR3. On the other hand, when the delay time from the rising of the clock signal CK to the rising of the delayed clock signal CKD becomes smaller than T/2, a frequency-multiplied signal CK2C as shown in FIG. 18B is obtained from the EX-OR circuit EXR3.
Both of these frequency-multiplied signals CK2B and CK2C are greatly deviated from the duty ratio of 50%. Namely, there is a problem in which a stable pulse width cannot be obtained.
In order to overcome this problem, many inventions have been applied for patent. One example of the inventions for overcoming the problem is disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-04-105413 (the content of which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-04-105413 is available from the Japanese Patent Office and the content of the English abstract of JP-A-04-105413 is also incorporated by reference in its entirety into this application).
Referring to FIG. 19, there is shown a circuit diagram of one example of the semiconductor delay circuit disclosed in JP-A-04-105413. This delay circuit is different from the prior art shown in FIG. 18A in that a timing adjusting circuit TCT is inserted between a variable delay circuit VDL composed of a group of cascaded delays DL and one input of an EX-OR circuit EXR4 having the other input connected to receive a pulse input signal PIN.
The timing adjusting circuit TCT includes a multiplexor MPX having an output terminal Y connected to the one input of an EX-OR circuit EXR4 and a plurality of input terminals DO to Dn connected to receive an input signal dO branched from the pulse input signal PIN for the delay group DL, a plurality of signals d1 to d(n-1) which are obtained from the delay group DL and which are deviated from one another in timing, and a signal dn outputted from the final stage of the delay group DL. A plurality of control terminals of the multiplexor MPX is connected to parallel outputs of a shift register SFR, respectively. A data input of the shift register SFR is connected to receive a serial data SI, and a clock input of the shift register SFR is connected to receive a shift clock SCK.
In this prior art, the high level pulse width can be adjusted to a desired value, by supplying the EX-OR circuit EXR4 with an output "di1" of the multiplexor MPX obtained by delaying only the timing of the pulse input signal PIN by the delay group DL. Namely, by setting the delay time of the delayed signal dn at a relatively long value, a suitable delayed signal having a delay time shorter than that of the delayed signal dn is selected by the multiplexor MPX in order to compensate for fluctuation in the delay time caused by the fluctuation in a manufacturing process.
Referring to FIG. 20, there is shown a circuit diagram of another example of the semiconductor delay circuit disclosed in JP-A-04-105413. This delay circuit is different from the prior art shown in FIG. 19 in that a D-type flipflop FF5 is used in place of the EX-OR circuit EXR4 and an erasable programmable ROM EPROM is used in place of the shift register SFR. Namely, an output "di2" of the timing adjusting circuit TCT is connected to a D input of the D-type flipflop FF5, and a reference clock CKI is supplied to a clock input of the D-type flipflop FF5.
The timing adjusting circuit TCT is so constructed that a signal d0 obtained from the pulse input signal DIN and a plurality of signals d1 to dn obtained from the delay group DL and deviated from one another in timing, are supplied to the multiplexor MPX, and one of these signals do to dn is selected by the multiplexor MPX and outputted as the output signal "di2". The multiplexor MPX is set by writing data into the erasable programmable ROM EPROM
Thus, the high level pulse width can be adjusted to a desired value, by supplying the D-type flipflop with the output "di2" of the multiplexor MPX obtained by delaying only the timing of the pulse input signal DIN by the delay group DL.
However, the above mentioned prior art frequency multiplying circuits have the following problems:
A first problem is that the duty ratio of the obtained frequency-multiplied signal varies. The reason for this is as follows:
When the delay circuit is constituted of cascaded inverters, the total delay amount is determined by a product of the delay amount of one inverter by the number of the cascaded inverters. However, because of fluctuation in a manufacturing process and variation in operating environment such as fluctuation of the power supply voltage, the delay amount of each inverters varies, so that the delay time as designed cannot be obtained. As a result, the duty ratio of the frequency-multiplied signal varies.
A second problem is that it cannot follow the fluctuation of the power supply voltage after completion of the adjustment The reason for this is as follows,
In the prior art example configured to stabilize the duty ratio, namely, the pulse width, of the frequency-multiplied signal, at an initial setting time, the delay amount is determined by the timing adjusting circuit including the multiplexor therein, and the control signal supplied to the multiplexor for determining the delay amount is fixed. Therefore, the frequency-multiplying circuit cannot follow an unexpected variation of the power supply voltage in an operation of the frequency-multiplying circuit.
A third problem is that it is necessary to initialize the delay amount and to supply an input signal to the multiplexor for setting the delay amount. The reason for this is as follows:
In the prior art examples disclosed in the above referred Japanese patent publication, the delay amount is determined by the multiplexor and the others. The control signal for the multiplexor is given from the EPROM or an external signal. The setting of the multiplexor is carried out by changing the delay amount, little by little, while monitoring the frequency-multiplied signal. In the case that the multiplexor is controlled by external signal, the set condition disappears at each time of the power-off, and therefore, it is necessary to conduct the setting at each time of the power-on.